Key Dates

Submission Deadline

May 12, 2017 AoE

Author Notification

June 16, 2017

Paper for Workshop

July 21, 2017


August 28/29, 2017

Paper Camera Ready

October 3, 2017

Call for Papers

in text format


Submit your paper here
(track UCHPC)

Hosting Conference

EuroPar 2017

Previous Workshops

2016 @ EuroPar'16
2015 @ EuroPar'15
2014 @ EuroPar'14
2013 @ EuroPar'13
2012 @ EuroPar'12
2011 @ EuroPar'11
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08


The workshop takes place on Tuesday, August 29, 2017 in room A4 in the same building as the Euro-Par conference, which is the Technical School of Engineering of the University of Santiago de Compostela ( map at Google Maps). For further information, have a look at the EuroPar 2017 website.

9:00 Workshop opening
by Josef Weidendorfer, Jens Breitbart
9:15 - 10:30 Session 1
Chair: Josef Weidendorfer
9:15 Keynote (more...)
Co-Designing HPC Architectures and the Runtime System
by Miquel Moreto, Barcelona Supercomputing Center and UPC (Slides)
10:05 Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model using Reconfigurable Hardware in Invasive Computing
by Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat and Michael Bader (Slides)
10:30 (coffee break)
11:00 - 12:50 Session 2
Chair: Jens Breitbart
11:00 Linking Application Description with Efficient SIMD Code Generation for Low-Precision Signed-Integer GEMM
by Günther Schindler, Manfred Mücke and Holger Fröning (Slides)
11:25 Accelerating the 3-D FFT using a heterogeneous FPGA architecture by Matthew Anderson, Maciej Brodowicz, Martin Swany and Thomas Sterling (Slides)
11:50 Evaluation of a Floating-point Intensive Kernel on FPGA - A Case Study of Geodesic Distance Kernel
by Zheming Jin, Hal Finkel, Kazutomo Yoshii and Franck Cappello (Slides)
12:15 Design Simulation Tool for Silicon Integrated Photonics Towards Exascale Systems
by Juan-José Crespo, Francisco Alfaro and Jose L. Sanchez (moved from PISCES workshop) (Slides)
12:40 Best Paper Award Ceremony and Workshop Closing


Miquel Moreto, Barcelona Supercomputing Center/UPC:
Co-Designing HPC Architectures and the Runtime System

Abstract: In the last decade, the traditional ways to keep the increase of hardware performance to the rate predicted by Moore's Law vanished. Multi-core processors helped maintaining performance improvements for a while, but they still have to face multiple problems in terms of power consumption, programmability, resilience and memory. To overcome these challenges, a promising approach is to give more responsibility to the runtime system and to let it tightly collaborate with the hardware. In fact, we believe that the runtime system has to drive the design of future multi-cores architectures. In this talk, we will introduce an approach towards a Runtime-Aware Architecture, a massively parallel architecture designed from the runtime's perspective.

Miquel Moreto is a senior researcher at Barcelona Supercomputing Center (BSC) and an adjunct lecturer at UPC, Spain. He received the BS and MS degrees in mathematics and electrical engineering from UPC, and the PhD degree in 2010 in the Computer Architecture Department at the same university. He was a Fulbright postdoctoral fellow at the International Computer Science Institute (ICSI), affiliated with UC Berkeley (USA) from 2012 to 2013. In 2013, he joined the BSC to work on the ERC-funded project RoMoL and the Mont-Blanc 3 H2020 European project. His research interests include studying shared resources in multithreaded architectures and hardware-software co-design for future massively parallel systems.