Key Dates

Submission Deadline

May 12, 2017 AoE

Author Notification

June 16, 2017

Paper for Workshop

July 21, 2017


August 28/29, 2017

Paper Camera Ready

October 3, 2017

Call for Papers

in text format


Submit your paper here
(track UCHPC)

Hosting Conference

EuroPar 2017

Previous Workshops

2016 @ EuroPar'16
2015 @ EuroPar'15
2014 @ EuroPar'14
2013 @ EuroPar'13
2012 @ EuroPar'12
2011 @ EuroPar'11
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08


Deadline extended to May 12, 2017.


Recent issues with the power consumption of conventional HPC hardware results in both new interest in accelerator hardware and in usage of mass-market hardware originally not designed for HPC. The most prominent examples are GPUs, but FPGAs, DSPs and embedded designs are also possible candidates to provide higher power efficiency, as they are used in energy-restriced environments, such as smartphones or tablets. The so-called "dark silicon" forecast, i.e. not all transistors may be active at the same time, may lead to even more specialized hardware in future mass-market products. Exploiting this hardware for HPC can be a worthwhile challenge.

As the word "UnConventional" in the title suggests, the workshop focuses on usage of hardware or platforms for HPC, which are not (yet) conventially used today, and may not be designed for HPC in the first place. Reasons for its use can be raw computing power, good performance per watt, or low cost in general. To address this unconventional hardware, often, new programming approaches and paradigms are required to make best use of it. Another focus of the workshop is on innovative, (yet) unconventional new programming models, and algorithms (e.g. Big Data) exploiting unconventional HPC hardware or software.

To this end, UCHPC tries to capture solutions for HPC which are unconventional today but could become conventional and significant tomorrow, and thus provide a glimpse into the future of HPC.


The goal of this workshop is to present research exploring currently unconventional techniques for HPC and their benefits. UCHPC also covers according programming models, compiler techniques, and tools. Thus, suggested topics for papers include, but are not limited to the following:
  • Innovative use of hardware and software unconventional for HPC
  • HPC applications in connection with HPC on GPUs (GPGPU), low power/embedded processors, FPGAs, Intel's Xeon Phi architecture, Tilera's tile-based many-core processors, AMDs HSA/hUMA concept, Processing in Memory (PIM), accelerators, etc.
  • Cluster/Grid solutions using unconventional hardware, e.g. clusters of game consoles, nodes using GPUs, Low Power/Embedded Processors, MPSoCs, new many-cores from Intel and/or ARM designs, Mac Minis/AppleTVs, FPGAs etc.
  • Heterogeneous computing on hybrid platforms
  • Performance and scalability studies in HPC using unconventional hardware
  • Reconfigurable Computing for HPC
  • Performance modeling, analysis and tools for HPC with unconventional hardware
  • (Yet) Unconventional programming models for HPC, including PGAS, task-based or data-flow concepts (and supporting tools)
  • Big data and/or deep learning using unconventional HPC hardware or software

Paper Submission, Registration, and Publication

Submissions in PDF format should be between 10 – 12 pages in the Springer LNCS style, which can be downloaded from the Springer Web site. The 12 pages limit is a hard limit. It includes everything (text, figures, references). On acceptance, at least one author is required to register for workshop attendance at Euro-Par 2017 and present the paper in the workshop.

Login in to the Euro-Par 2017 Workshop submission server (author role), select the track "UCHPC - UnConventional High Performance Computing", and submit your paper in PDF format. It must not be simultaneously submitted to the main conference or any other publication outlet.

For the workshop, we will prepare hand-outs with the revised papers. These will be published after the conference in the workshop proceedings of Euro-Par 2017, part of the LNCS series of Springer.

Best Paper Award

This year, our Best Paper Award goes to "Accelerating the 3-D FFT using a heterogeneous FPGA architecture" by Matthew Anderson, Maciej Brodowicz, Martin Swany and Thomas Sterling. Congratulations!

As in recent years, we had a price together with a trophae for the best paper award. This year, this was a PYNQ board with a Zynx XC7Z020 SoC, sponsored by Xilinx. We were happy to hand out this price to Matthew Anderson, the presenter of the paper (on the right in the picture).